%\singlespacing -- NOT in HPCA

Spin-Transfer Torque RAM (STT-RAM) is an emerging non-volatile memory (NVM)
technology that has the potential to replace the conventional
on-chip SRAM caches for designing a more efficient memory hierarchy for
multi-core architectures. Although the high density, low leakage and high endurance are attractive features of STT-RAM,
the latency and energy overhead associated with write operations are major obstacles for being competitive with the SRAM.
Our study shows that the non-volatility feature with years of data-retention time for STT-RAM technology is not necessary for its usage in on-chip cache, since the refresh times of cache data are usually in  \it{$\mu$s} (for L1 cache) or $ms$ (for L2 cache) range. 
Thus,  we propose to trade-off the non-volatility (data-retention time) of STT-RAM
for better write performance/energy for designing STT-RAM-based L2 cache.
The paper addresses several critical design issues such as how we decide on a suitable retention time for last level cache,
what the relationship between retention time and write latency is,
and how we architect the cache hierarchy with volatile STT-RAM.
%Through an extensive execution driven analysis of the inter-write time of several PARSEC and SPEC 2006 benchmarks, we
%observe that retention time in the order of 10-40 ms is a good design point to handle most of the
%writes.
We study two
data-retention time relaxation cases, one with data-retention time of  $1sec$, which satisfies the refresh time requirement of typical cache blocks; and the other one with data-retention time of $10ms$, which is a more aggressive design for better performance/energy gains, but requires a data refreshing mechanism.
For the aggressive $10ms$ retention time design, we propose a selective block refreshing scheme for the
cache blocks that have a higher refresh time than the STT-RAM retention time to avoid any data loss.
%with a per block $2$-$bit$ counter, temporarily save a limited number of MRU blocks in a buffer,
%and write-back the rest of the dirty blocks to avoid any data loss.
%are not in first seven MRU slots.
%The blocks in these slots are copied to
%a per bank small buffer and again copied back to the respective slots.
Our experiments with a four-core architecture with an SRAM-based L1 cache and volatile STT-RAM-based L2 cache
indicate that not only we can eliminate the long write latency overhead of the NVM STT-RAM, but also can provide
on an average $10$-$12\%$ improvement in performance compared to the traditional SRAM-based
design, while reducing the energy consumption by 60\%.

